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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, pl ease contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 19-5568; rev 1; 9/11 general description the max5980 is a quad, power-sourcing equipment (pse) power controller designed for use in ieee ? 802.3at/af-compliant pse. this device provides powered device (pd) discovery, classification, current limit, and load disconnect detection. the device supports both fully automatic operation and software programmability. the device also supports new 2-event classification and class 5 for detection and classification of high-power pds. the device supports single-supply operation, pro- vides up to 70w t o each port (class 5 enabled), and still provides high-capacitance detection for legacy pds. the device features an i 2 c-compatible, 3-wire serial interface, and is fully software configurable and pro- grammable. the device provides instantaneous readout of port current and voltage through the i 2 c interface. the device?s extensive programmability enhances system flexibility, enables field diagnosis, and allows for uses in other, nonstandard applications. the device is available in a space-saving, 32-pin tqfn (5mm x 5mm) power package and is rated for the auto- motive (-40 n c to +105 n c) temperature range. features s ieee 802.3at/af compliant s 0.25 i current-sensing resistor s up to 70w per port for pse applications s 9-bit port current and voltage monitoring s i 2 c-compatible, 3-wire serial interface s supports single-supply operation s high-capacitance detection for legacy devices s supports dc load-removal detections s space-saving, 32-pin tqfn (5mm x 5mm) power package applications pse-icm power-sourcing equipment (pse) switches/routers midspan power injectors + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. simplified operating circuit ordering information ieee is a registered service mark of the institute of electrical and electronics engineers, inc. out1 port 1 output port 2 output gate1gate2 out3 out4 gate3 a3 a2 a1 a0 en_cl5 midspan gate4 sense4 sense3 sense2 sense1 svee2 svee1 v ee dgnd scl sdaout sdain out2 auto en en v dd agnd -54v -54v max5980 port 3 output port 4 output int part temp range pin-package MAX5980GTJ+ -40 n c to +105 n c 32 tqfn-ep* downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 2 stresses beyond those listed under ?absolute maximu m ratings? may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to v ee , unless otherwise noted.) agnd ....................................................................-0.3v to +80v dgnd, svee_ ......................................................-0.3v to +0.3v v dd ........................ -0.3v to the lower (v agnd + 0.3v) and +4v out_ ....................................................-0.3v to (v agnd + 0.3v) gate_, sense_ ....................................................-0.3v to +22v a3, a2, a1, a0, midspan, en_cl5, auto, int , scl, sdain, sdaout, en to dgnd ..........-0.3v to +6v maximum current into int and out .................................20ma maximum current into out_ .......................internally regulated continuous power dissipation (t a = +70 n c) 32-pin tqfn (derate 34.5mw/ n c above +70 n c) ....2758.6mw package thermal resistance (note 1) b ja ............................................................................. +29 n c/w b jc ........................................................................... +1.7 n c/w operating temperature range ........................ -40 n c to +105 n c storage temperature range ............................ -65 n c to +150 n c junction temperature .....................................................+150 n c lead temperature (soldering, 10s) ................................+300 n c soldering temperature (reflow) ......................................+260 n c electrical characteristics (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, and default register settings. currents are positive when entering the pin, and negative otherwise.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units power supplies operating voltage range v agnd v agnd - v ee 32 60 v supply currents i ee v out_ = v sense_ = v ee ; int , sdaout, and all logic inputs unconnected; v scl = v sdain = v dd ; measured at agnd in power mode after gate_ pullup 5 7 ma gate driver and clamping gate_ pullup current i pu power mode, gate drive on, v gate_ = v ee -40 -50 -60 f a gate_ pulldown current i pdw port shdn mode enabled; v gate_ = v ee + 10v 40 f a strong pulldown current i pds v sense_ = 500mv, v gate_ = v ee + 2v 25 ma external gate drive v gs v gate_ - v ee , power mode, gate-drive on 8.5 9.5 10.5 v current limit and overcurrent current-limit clamp voltage v su_lim maximum v sense_ allowed during current-limit conditions, v out_ = 0v (note 3) i lim_ register set to 80h, class 0?3 101 106.25 111.5 mv i lim_ register set to c0h, class 4 200 212.5 225 i lim_ register set to c0h, class 5 405 430 455 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 3 electrical characteristics (continued) (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, and default register settings. currents are positive when entering the pin, and negative otherwise.) (note 2) parameter symbol conditions min typ max units overcurrent threshold after startup v cut overcurrent v sense_ threshold allowed for t p t fault after startup, v out_ = 0v i cut_ register set to 14h, class 0 and 3 89 93.75 98.5 mv i cut_ register set to 22h, class 4 178 187.5 197 i cut_ register set to 22h, class 5 356 375 394 foldback initial voltage v flbk_st v agnd - v out_ above which the current-limit trip voltage starts folding back i lim register set to 80h 32 v i lim register set to c0h 18 foldback final voltage v flbk_end v agnd - v out_ above which the current limit reaches v th_fb 46 v minimum foldback current-limit threshold v th_fb v out_ = v agnd = 60v 35 mv sense_ input bias current v sense_ = v ee -2 f a supply monitorsv ee undervoltage lockout v ee_uvlo v agnd - v ee , v agnd - v ee increasing 29 v v ee undervoltage lockout hysteresis v ee_uvloh ports shut down if: v agnd - v ee < v ee_uvlo - v ee_uvloh 3 v v ee overvoltage lockout v ee_ov ports shut down if: v agnd - v ee > v ee_ov , v agnd - v ee increasing 62 v v ee overvoltage-lockout hysteresis v ee_ovh 1 v v ee undervoltage v ee_uv v ee_uv event bit sets if: v agnd - v ee < v ee_uv , v agnd - v ee increasing 40 v v dd output voltage v dd i dd = 0 to 10ma 3.0 3.3 3.6 v v dd undervoltage lockout v dd_uvlo 2 v thermal-shutdown threshold t shd port is shut down and device resets if the junction temperature exceeds this limit, temperature increasing (note 4) +140 n c thermal-shutdown hysteresis t shdh temperature decreasing (note 4) 20 n c output monitor out_ input current i bout v out_ = v agnd , during idle 2 f a v agnd - v ee = 48v, v out_ = v ee , during power-on mode -70 idle pullup resistance at out_ r dis detection and classification off, port shut down 0.7 1 1.25 m i pgood high threshold pg th v out_ - v ee , out_ decreasing 1.5 2.0 2.5 v downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 4 electrical characteristics (continued) (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, and default register settings. currents are positive when entering the pin, and negative otherwise.) (note 2) parameter symbol conditions min typ max units pgood hysteresis pg hys 220 mv pgood low-to-high glitch filter t pgood time v out_ - v ee has to exceed pgth to set the pgood_ bit in register 10h 2 4 ms load disconnect dc load disconnect threshold v dcth minimum v sense_ allowed before disconnect (dc disconnect active), v out_ = 0v 1.25 1.875 2.5 mv load disconnect time t disc time from v sense_ < v dcth to gate shutdown (note 5) 300 400 ms detectiondetection probe voltage (first phase) v dph1 v agnd - v det during the first detection phase 3.8 4 4.2 v detection probe voltage (second phase) v dph2 v agnd - v det during the second detection phase 8.8 9.1 9.4 v current-limit protection i dlim v out_ = v agnd , current measured through out_ during detection 1.50 2 ma short-circuit threshold v dcp if v agnd - v out_ < v dcp after the first detection phase, a short circuit to agnd is detected 1.5 v open-circuit threshold i d_open first point measurement current threshold for open condition 12.5 f a resistor detection window r dok (note 5) 19 26.5 k i resistor rejection window r dbad detection rejects lower values 15.2 k i detection rejects higher values 32 classification classification probe voltage v cl v agnd - v out_ during classification 15.5 20 v current-limit protection i cl_lim v out_ = v agnd , current measured through out_ 65 75 86 ma classification event timing t cl_e 14 18 22 ms mark event voltage v mark v agnd - v det during mark event 8 9.6 v mark event current limit i mark_lim v det = v agnd , during mark event measure current through det 34 40 46 ma mark event timing t mark_e 7 9 11 ms classification current thresholds i cl classification current thresholds between classes class 0, class 1 5.5 6.5 7.5 ma class 1, class 2 13.0 14.5 16.0 class 2, class 3 21 23 25 class 3, class 4 31 33 35 class 4 upper limit (note 6) 45 48 51 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 5 electrical characteristics (continued) (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, and default register settings. currents are positive when entering the pin, and negative otherwise.) (note 2) parameter symbol conditions min typ max units digital inputs/outputs (voltages referenced to v ee ) digital input low v il 0.8 v digital input high v ih 2 v internal input pullup/pulldown resistor r din pullup (pulldown) resistor to v dd (dgnd) to set default level 25 50 75 k i open-drain output low voltage v ol i sink = 10ma 0.4 v open-drain leakage i ol open-drain high impedance, v out_ = 3.3v 1 f a scl, sdain input leakage i dl input connected to the pull voltage 1 f a hardware reset pulse width minimum low pulse duration on en to lead to a hardware reset event 120 f s timing startup time t start time during which a current limit set by v su_lim is allowed, starts when the gate_ is turned on 50 60 70 ms fault time t fault time allowed for an overcurrent fault set by v flt_lim after startup 50 60 70 ms current limit t lim time during after startup (note 7) 50 60 70 ms port_ turn-off time t off minimum delay between any port turn-off, does not apply in a reset case 0.1 ms detection reset time time allowed for the port voltage to reset before detection starts 80 ms detection time t det maximum time allowed before detection is completed 330 ms midspan mode detection delay t dmid 2 s classification time t class time allowed for classification 19 25 ms v ee_uvlo turn-on delay t dly time v agnd must be above the v ee_uvlo threshold before the device operates 2 4 ms restart timer t restart time the device waits before turning on after an overcurrent fault, midspan disabled 0.8 0.96 1.1 s startup sequence delay t seq time between any port power-up in auto mode 0.5 s adc performance (power-on mode)resolution 9 bits offset error voltage reading t a = -5 c to +85 c 2.5 lsb t a = -40 c to +105 c 3 current reading t a = -5 c to +85 c 2.5 t a = -40 c to +105 c 3 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 6 note 2: production testing done at +25 n c. overtemperature limits are guaranteed by design and not production tested. note 3: the current-limit thresholds are programmed through the i 2 c interface (see the register map and description section and table 41). note 4: functional test is performed over thermal shutdown entering test mode. note 5: r dok = (v out2 - v out1 )/(i out2 - i out1 ). v out1 , v out2 , i out1 , and i out2 represent the voltage at out_ and the current into out_ during phase 1 and 2 of the detection, respectively. note 6: if class 5 is enabled, this value is the classification current threshold from class 4 to class 5, and classification currents between 51ma and i cl_lim will be classified as class 5. note 7: default value. the fault timer can be reprogrammed through the i 2 c interface (tlim_[3:0]). note 8: guaranteed by design. not subject to production testing. electrical characteristics (continued) (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, and default register settings. currents are positive when entering the pin, and negative otherwise.) (note 2) parameter symbol conditions min typ max units gain error gain error voltage t a = -5 c to +85 c -0.5 +4 % t a = -40 c to +105 c -1 +4.5 gain error current t a = -5 c to +85 c -2 +2 t a = -40 c to +105 c -2.5 +2.5 v ee voltage accuracy v agnd - v ee = 48v t a = -5 c to +85 c -0.5 +4.5 % t a = -40 c to +105 c -0.5 +5 integral nonlinearity inl 1 lsb differential nonlinearity dnl 1 lsb current reading range classes 0?4 1 a class 5 2 current lsb step size classes 0?4 1.956 ma class 5 3.912 voltage reading range all classes 95.6 v voltage lsb step size all classes 187 mv timing characteristics (3-wire fast mode) serial clock frequency f scl 10 400 khz bus free time between a stop and start condition t buf 1.3 f s hold time for a start condition t hd, sta 0.6 f s low period of the scl clock t low 1.3 f s high period of the scl clock t high 0.6 f s setup time t su, sta start and stop conditions 0.6 f s data hold time t hd, dat receive 0 ns transmit 100 300 data in setup time t su, dat 100 ns cumulative clock low extend time t low_ext 25 ms fall time of sdaout transmitting t f (note 8) 250 ns setup time for stop condition t su, sto 0.6 f s pulse width of spike suppressed t sp (note 8) 30 ns downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 7 typical operating characteristics (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, endpoint mode, and default register settings with a class 0 pd, unless otherwise noted.) analog supply current vs. analog supply voltage max5980 toc01 v agnd - v ee (v) supply current (ma) 56 52 48 44 40 36 2.4 2.8 3.2 3.62.0 32 60 auto modeno pds connected t a = +105c t a = +25c t a = -40c digital supply regulated voltage vs. load current max5980 toc02 total current load (ma) v dd output voltage (v) 15 10 5 3.0 3.1 3.2 3.3 3.42.9 0 20 analog supply undervoltage lockout vs. temperature max5980 toc03 temperature (c) undervoltage lockout (v) 85 60 35 10 -15 28.5 29.0 29.5 30.028.0 -40 110 v agnd - v ee rising analog supply overvoltage lockout vs. temperature max5980 toc04 temperature (c) overvoltage lockout (v) 85 60 35 10 -15 61.5 62.0 62.5 63.061.0 -40 110 v agnd - v ee rising gate overdrive voltage vs. analog supply voltage max5980 toc05a v agnd - v ee (v) gate overdrive (v) 56 52 48 44 40 36 9.1 9.2 9.3 9.4 9.59.0 32 60 gate overdrive voltage vs. temperature max5980 toc05b temperature (c) gate overdrive (v) 85 60 35 10 -15 9.0 9.1 9.2 9.3 9.4 9.58.9 -40 110 current-limit sense_ threshold vs. analog supply voltage max5980 toc06 current-limit sense_ threshold (mv) 92.9 93.0 93.1 93.292.8 v agnd - v ee (v) 56 52 48 44 40 36 32 60 class 0 foldback current-limit sense_ threshold vs. port output voltage v out_ - v ee (v) v sense - v ee (mv) 40 30 20 10 50 100 150 200 250 0 50 max5980 toc07 class 4 classes 0?3 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 8 typical operating characteristics (continued) (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, endpoint mode, and default register settings with a class 0 pd, unless otherwise noted.) dc load disconnect sense_ threshold vs. temperature max5980 toc08 temperature (c) disconnect threshold (mv) 85 60 35 10 -15 1.6 1.8 2.0 2.2 2.41.4 -40 110 overcurrent timeout (r load = 240 i to 140 i ) max5980 toc09 v agnd - v out_ 50v/divv gate_ 10v/div i out_ 200ma /div 20ms/div 0v 0ma 0v current-limit timeout (r load = 240 i to 75 i ) max5980 toc10 v agnd - v out_ 50v/divv gate_ 10v/div i out_ 200ma /div 20ms/div 0v 0ma 0v current-limit transient response (r load = 240 i to 75 i ) max5980 toc11 v agnd - v out_ 50v/divv gate_ 10v/div i out_ 200ma /div 400s/div 0v 0ma 0v output short-circuit timeout max5980 toc12 v agnd - v out_ 20v/divv gate_ 10v/div i out_ 200ma /div 20ms/div 0v 0ma 0v output short-circuit response time max5980 toc13 v agnd - v out_ 20v/divv gate_ 10v/div i out_ 10a /div 10s/div 0v0a 0v downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 9 typical operating characteristics (continued) (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, endpoint mode, and default register settings with a class 0 pd, unless otherwise noted.) en to hardware power-down delay max5980 toc14 v agnd - v out_ 50v/divv gate_ 5v/divv en 2v/div 100s/div 0v0v 0v zero current detection max5980 toc15 v gate_ 10v/div i out_ 100ma/div 100ms/div 0v 0ma 0v v agnd - v out_ 20v/div overcurrent restart delay max5980 toc16 v gate_ 10v/div i out_ 200ma/div 400ms/div 0v 0ma 0v v agnd - v out_ 20v/div startup with valid pd (25k i , 0.1f, class 3) max5980 toc17 v gate_ 10v/div i out_ 200ma/div 100ms/div 0v 0ma 0v v agnd - v out_ 20v/div detection with invalid pd (15k i and 0.1f) max5980 toc18a i out_ 1ma/div 100ms/div 0v 0ma v agnd - v out_ 5v/div detection with invalid pd (33k i and 0.1f) max5980 toc18b i out_ 1ma/div 100ms/div 0v 0ma v agnd - v out_ 5v/div downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 10 typical operating characteristics (continued) (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, endpoint mode, and default register settings with a class 0 pd, unless otherwise noted.) detection with invalid pd (25k i and 10f) max5980 toc18c i out_ 1ma/div 40ms/div 0v 0ma v agnd - v out_ 1v/div detection with invalid pd (open circuit) max5980 toc18d i out_ 1ma/div 100ms/div 0v 0v 0ma v agnd - v out_ 5v/divv gate_ 10v/div startup in midspan mode with valid pd (25k i , 0.1f, class 3) max5980 toc19 i out_ 200ma/div 100ms/div 0v 0v 0ma v agnd - v out_ 20v/divv gate_ 10v/div detection in midspan mode with invalid pd (15k i and 0.1f) max5980 toc20a i out_ 1ma/div 400ms/div 0v 0ma v agnd - v out_ 5v/div downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 11 typical operating characteristics (continued) (v agnd = 32v to 60v, v ee = v dgnd = 0v, t a = -40 n c to +105 n c. all voltages are referenced to v ee , unless otherwise noted. typical values are at v agnd = 54v, t a = +25 n c, endpoint mode, and default register settings with a class 0 pd, unless otherwise noted.) detection in midspan mode with invalid pd (33k i and 0.1f) max5980 toc20b i out_ 1ma/div 400ms/div 0v 0ma v agnd - v out_ 5v/div detection with out_ shorted to agnd max5980 toc21 i out_ 1ma/div 40ms/div 0v 0v 0ma v agnd - v out_ 5v/divv gate_ 10v/div classification with class 0 to 3 pds max5980 toc22 i out_ 10ma/div 40ms/div 0v 0ma v agnd - v out_ 10v/div class 3class 2 class 1 class 0 2-event classification with class 4 and 5 pds max5980 toc23 i out_ 20ma/div 40ms/div 0v 0ma v agnd - v out_ 10v/div class 5class 4 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 12 pin configuration pin description 24 23 22 21 20 19 18 1 2 3 4 5 6 7 10 11 12 13 14 15 16 31 30 29 28 27 26 25 max5980 tqfn top view out1 gate1 n.c. svee1 en_cl5 auto midspan 32 int *connect to v ee *ep sense1 out2 gate2 sense2 out3 gate3 sense3 17 out4 gate4sense4 agnd n.c. v dd v ee svee2 9 dgnd a2 a1 8 a3 a0 en sdain sdaout scl + pin name function 1 scl 3-wire serial interface input clock line. referenced to dgnd. connect to dgnd if the i 2 c interface is not used. 2 sdaout serial interface data line output. referenced to dgnd. connect to dgnd if the i 2 c interface is not used. 3 sdain serial interface data line input. referenced to dgnd. connect to dgnd if the i 2 c interface is not used. 4 en en input. referenced to dgnd. connect en to v dd externally through a pullup resistor to enable normal operation. see the hardware power-down section for details. 5, 6, 7, 8 a0, a1, a2, a3 slave address bits 0, 1, 2, 3 (respectively). referenced to dgnd. the slave address bits are used to form bits 3, 2, 1, and 0 of the device address (0:1:0:a3:a2:a1:a0; see table 3). the slave address bits are internally pulled up to v dd . leave them unconnected to use the default device address (0101111). connect one or more to dgnd to change the device address. the slave address is latched-in after the device is powered up or after a reset condition. 9 dgnd digital low-side supply input. connect to v ee externally. 10 svee2 port 3/4 current-sense negative terminal input. use kelvin-sensing technique in pcb layout for best accuracy current sensing. downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 13 pin description (continued) pin name function 11 v ee analog low-side supply input. bypass with an external 100v, 0.1 f f ceramic capacitor between agnd and v ee . 12 v dd digital high-side supply output. bypass with an external rc network; see the v dd power supply section for details. 13, 27 n.c. no connection. not internally connected. leave n.c. unconnected. 14 agnd analog high-side supply input 15, 18, 21, 24 sense4, sense3, sense2, sense1 current-sense positive terminal inputs. connect to the source of the external power mosfet and connect a 0.25 i current-sense resistor between sense_ and svee _ . use kelvin-sensing technique in pcb layout for best accuracy current sensing. 16, 19, 22, 25 gate4, gate3, gate2, gate1 port_ mosfet gate drivers. connect gate_ to the gate of the external power mosfet (see the typical operating circuit ). 17, 20, 23, 26 out4, out3, out2, out1 port output voltage senses. connect out_ to the port output. 28 svee1 port 1/2 current-sense negative terminal input. use kelvin sensing technique in pcb layout for best accuracy current sensing. 29 en_cl5 class 5 enable input. referenced to dgnd. en_cl5 is internally pulled down to dgnd. leave unconnected to disable the classification for class 5 devices (ieee 802.3at-compliant mode). connect en_cl5 to v dd to enable the classification of class 5 devices. en_cl5 is latched in after the device is powered up or after a reset condition. 30 auto auto/shutdown mode input. referenced to dgnd. auto is internally pulled up to v dd . leave unconnected to put the device into auto mode by default. connect auto to dgnd instead to set the default mode to shutdown. in either configuration, the software can change the operating mode of the device. auto is latched in after the device is powered up or after a reset condition. 31 midspan detection collision avoidance logic input. referenced to dgnd. midspan is internally pulled up to v dd . leave unconnected to activate midspan mode, or connect to dgnd to disable this function. midspan is latched in after the device is powered up or after a reset condition. 32 int open-drain interrupt output. referenced to dgnd. int is pulled low whenever an interrupt is sent to the microcontroller. see the interrupt section for details. connect to dgnd if the i 2 c interface is not used. ? ep exposed pad. ep is internally connected to v ee . connect ep to v ee externally. downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 14 functional diagram current sensing midspan auto analog bias and supply monitors internalreferences and supplies agnd v ee voltagesensing gate-drive control out_ powerenable foldback control threshold settings current limit, overcurrent, and open-circuit sensing, and foldback control sdain sdaout scl en_cl5 dgnd v dd digital bias en a3?a0 gate_ sense_ fast discharge svee1 svee2 sense_ v ee serial port interface (spi) voltage probing and current-limit control register file port state machine (sm) detection and classification control 9-bit adcconverter central logic unit (clu) max5980 int downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 15 detailed description the max5980 is a quad pse power controller designed for use in ieee 802.3at/af-compliant pse. this device provides pd discovery, classification, current limit, and load disconnect detections. the device supports both fully automatic operation and software programmability. the device also supports new 2-event classification and class 5 for detection and classification of high-power pds. the device supports single-supply operation, pro- vides up to 70w to each port (class 5 enabled), and still provides high-capacitance detection for legacy pds. the device features an i 2 c-compatible, 3-wire serial interface, and is fully software configurable and pro- grammable. the device provides instantaneous readout of port current and voltage through the i 2 c interface. the device provides input undervoltage lockout (uvlo), input overvoltage lockout (ovlo), overtemperature pro- tection, and output voltage slew-rate limit during startup. reset the device is reset by any of the following conditions: 1) power-up/down. reset condition is asserted once v ee falls below the uvlo threshold. 2) hardware reset. to initiate a hardware reset, pull en low to dgnd for at least 100 f s. hardware reset clears once, en returns high to v dd , and all registers are set to their default states. 3) software reset. to initiate a software reset, write a logical 1 to the reset_ic register (r1ah[4]) any time after power-up. reset clears automatically, and all registers are set to their default states. 4) thermal shutdown. the device enters thermal shut- down at +140 n c. the device exits thermal shutdown and is reset once the temperature drops below 120 n c. during normal operation, changes to the address inputs, midspan, en_cl5, and auto are ignored, and they can be changed at any time prior to a reset state. at the end of a reset event, the device latches in the state of these inputs. port reset set reset_p_ (r1ah[3:0]) high anytime during normal powered operation to turn off port_, disable detection and classification, and clear the port_ event and status registers. if a port is not powered, setting reset_p_ high for that port has no effect. individual port reset does not initiate a global device reset. midspan mode in midspan mode, the device adopts cadence timing during the detection phase. when cadence timing is enabled and a failed detection occurs, the ports wait at least 2s before attempting to detect again. midspan mode is activated by setting midspan high and then powering or resetting the device. alternatively, midspan mode can be software programmed individually for each port by setting midspan_ (r15h[3:0], table 23) to a logical 1. by default, the midspan input is internally pulled high, enabling cadence timing. force midspan low to disable this function. operation modes the device provides four operating modes to suit differ- ent system requirements. by default, auto mode allows the device to operate automatically at its default settings without any software. semiautomatic mode automatically detects and classifies devices connected to the ports, but does not power a port until instructed to by software. manual mode allows total software control of the device and is useful for system diagnostics. shutdown mode terminates all activities and securely turns off power to the ports. switching between auto, semiautomatic, and manual mode does not interfere with the operation of an out- put port. when a port is set into shutdown mode, all port operations are immediately stopped and the port remains idle until shutdown mode is exited. auto (automatic) mode by default, when the auto input is unconnected, the device enters auto mode after power-up or when the reset condition is cleared. to manually place a port into auto mode from any other mode, set the corresponding port mode bits (r12h[7:0]) to [11] (table 19). in auto mode, the device performs detection, classifica- tion, and powers up the port automatically if a valid pd is connected to the port. if a valid pd is not connected at the port, the device repeats the detection routine con- tinuously until a valid pd is connected. when entering auto mode after a reset condi- tion (state of auto input), the det_en_ and class_en_ bits (r14h[7:0], table 22) are set to hig h and stay high, unless changed by software. when ent er- ing auto mode from any other mode due to a software command (programmed with r12h[7:0], table 19, the det_en_ and class_en_ bits retain their previous st ate. downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 16 semiautomatic (semi) mode enter semiautomatic mode by setting the port operat ing mode (r12h, table 19) to [10]. when entering semi m ode, the det_en_ and class_en_ bits retain their previou s states. when the det_en_ and/or class_en_ bits are set to 1, the max5980 performs detection and/or classif ication repeatedly, but do not power up the port(s) automat ically. setting r19h[3:0] (pwr_on_, table 26) high turns on power to the port(s) if detection and classification has successfully completed. if a port is powered down while in semiautomatic mode, the corresponding det_en_ and class_en_ bits are reset to 0. manual mode enter manual mode by setting the port operating mode (r12h, table 19) to [01]. manual mode allows the soft- ware to dictate any sequence of operation. in manual mode, the detection/classification register (r14h, table 22) is set to 00h, and det_en_/class_en_ become pushbutton bits. a port will only perform a single detec- tion/classification cycle when det_en_/class_en_ are set high, and they are reset low after execution. pwr_on_ (r19h[3:0], table 26) has the highest prior- ity, and setting pwr_on_ high at any time causes the device to immediately enter the powered mode. setting det_en_ and class_en_ high at the same time causes detection to be performed first. once in the powered state, the device ignores det_en_ and class_en_ commands. shutdown mode to put a port into shutdown mode, set the correspond- ing port mode bits (r12h, table 19) to [00]. putting a port into shutdown mode immediately turns off port power, clears the event and status bits, and halts all port operations. in shutdown mode the serial interface is still fully active; however, all det_en_, class_en_, and pwr_on_ commands are ignored. pd detection during normal operation, the device probes the output for a valid pd. a valid pd has a 25k i discovery signature characteristic as specified in the ieee 802.3at/af stan- dard. table 1 shows the ieee 802.3at specification for a pse detecting a valid pd signature. after each detection cycle, the device sets det_ (r04h[3:0] and r05h[3:0], table 9) to 1 and reports the detection results in the detection status bits (see table 13). the det_ bits are reset to 0 when read through the cor (clear on read) register (r05h), or after a reset event. during detection, the device keeps the external mosfet off and forces two probe voltages through out_. the current through out_ is measured, as well as the volt- age difference from agnd to out_. a two-point slope measurement is used, as specified by the ieee 802.3at/ af standard, to verify the device connected to the port. the device implements appropriate settling times to reject 50hz/60hz power-line noise coupling. table 1. pse pi detection modes electrical requirements (ieee 802.3at) parameter symbol min max units additional information open-circuit voltage v oc ? 30 v in detection mode only short-circuit current i sc ? 5 ma in detection mode only valid test voltage v valid 2.8 10 v ? voltage difference between test points d v test 1 ? v ? time between any two test points t bp 2 ? ms this timing implies a 500hz maximum probing frequency slew rate v slew ? 0.1 v/ f s ? accept signature resistance r good 19 26.5 k i ? reject signature resistance r bad < 15 > 33 k i ? open-circuit resistance r open 500 ? k i ? accept signature capacitance c good ? 150 nf ? reject signature capacitance c bad 10 ? f f ? signature offset voltage tolerance v os 0 2.0 v ? signature offset current tolerance i os 0 12 f a ? downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 17 to prevent damage to non-pd devices, and to protect itself from an output short circuit, the device limits the current into out_ to less than 2ma (max) during pd detection. in midspan mode, after every failed detection cycle, the device waits at least 2.0s before attempting another detection cycle. high-capacitance detection high-capacitance detection for legacy pds is soft- ware programmable. to use the software to enable high-capacitance detection, set leg_en_ (port gpmd registers, table 39) to 1 during normal operation. if high- capacitance detection is enabled, pd signature capaci- tances up to 100 f f (typ) are accepted. power device classification (pd classification) during pd classification, the device forces a probe volt- age between 15v and 20v at out_ and measures the current into out_. the measured current determines the class of the pd. after each classification cycle, the device sets cls_ (r04h[7:4] and r05h[7:4], table 9) to 1 and re ports the classification results in the classification st atus bits (see table 13). the cls_ bits are reset to 0 when read through the cor (clear on read) register (r05h) or after a reset event. if en_cl5 is left unconnected, the device will classify the pd based on table 33-9 of the ieee 802.3at standard (see table 2). if the measured current exceeds 51ma, the device will not power the pd, but will report an over- current classification result and will return to idle state before attempting a new detection cycle. class 5 pd classification the device supports high power beyond the ieee 802.3at standard by providing an additional classifica- tion (class 5) if needed. to enable class 5, connect en_cl5 to v dd and initiate a global reset or use the soft- ware to individually enable class 5 classification for each port (r1ch[3:0], table 29). once class 5 is enabled, during classification, if the device detects currents in excess of the class 4 upper-limit threshold, the pd will be classified as a class 5 powered device. the pd is guaranteed to be classified as a class 5 device for any classification current from 51ma up to the classification current-limit threshold. the class 5 overcurrent threshold and current limit will be set automatically with icut_[5:0] and ilim_ (see tables 40 and 41). leave en_cl5 unconnected to disable class 5 detection and to be fully compliant to ieee 802.3at standard classification. table 2. pse classification of a pd (table 33-9 of the ieee 802.3at standard) measured i class (ma) classification 0 to 5 class 0 > 5 and < 8 may be class 0 or 1 8 to 13 class 1 > 13 and < 16 either class 1 or 2 16 to 21 class 2 > 21 and < 25 either class 2 or 3 25 to 31 class 3 > 31 and < 35 either class 3 or 4 35 to 45 class 4 > 45 and < 51 either class 4 or invalid downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 18 2-event pd classification if the result of the first classification event is class 0 to 3, then only a single classification event occurs as shown in figure 1. however, if the result is class 4 (or class 5), the device will perform a second classification event as shown in figure 2. between the classification cycles, the device performs a first and second mark event as required by the ieee 802.3at standard, forcing a -9.3v probing voltage at out_. powered state when the device enters a powered state, the t fault timer is reset and power is delivered to the pd. pgood_ (r10h[7:4], table 16) is set to 1 when the device enters the normal power condition. pgood_ immedi- ately resets to 0 whenever the power to the port is turned off. the power-good change bits, pg_chg_ (r02h[3:0], table 8) are set both when the port powers up and when it powers down. overcurrent protection a sense resistor, r sense_ , connected between sense_ and svee_ monitors the load current. under normal oper- ating conditions, the voltage across r sense_ (v rsense_ ) never exceeds the current-limit threshold, v su_lim . if v rsense_ exceeds v su_lim , an internal current-limiting circuit regulates the gate_ voltage, limiting the current to i lim = v su_lim /r sense_ . during transient conditions, if v rsense_ exceeds v su_lim by more than 500mv, a fast pulldown circuit activates to quickly recover from the current overshoot. during startup, if the current-limit con- dition persists, when the startup timer, t start , times out, the port shuts off, and the tstart_ bit is set (r08h[3:0] and r09h[3:0], table 11). in the normal powered state, the device checks for overcurrent conditions as determined by v cut . the t fault counter sets the maximum allowed continuous overcurrent period. the t fault counter increases when figure 1. detection, classification, and port power-up sequence v out_ - v agnd 80ms 19ms 150ms t det(2) t class t det(1) 150ms t -54v -18v -9.1v -4v 0v downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 19 v rsense_ exceeds v cut and decreases at a slower pace when v rsense_ drops below v cut . a slower decrement for the t fault counter allows for detecting repeated short-duration overcurrent conditions. when the counter reaches the t fault limit, the device powers the port down and asserts the corresponding tcut_ bit (r06h[3:0] and r07h[3:0], table 10). for a continu- ous overstress, a fault latches exactly after a period of t fault . v cut is programmable through the icut_ registers (table 40). if a port is powered down due to a current-limit condition, during normal operation, the device asserts the corresponding icv_ bit (r08h[7:4] and r09h[7:4], table 11) after power-off due to an overcurrent fault, the t fault timer is not immediately reset but starts decrementing at the same slower pace. the device allows a port to be powered on only when the t fault counter is at zero. this feature sets an automatic duty-cycle protection to the external mosfet to avoid overheating. high-power mode the device features individual, port programmable high- power settings. to enable the high-power configuration for a port, set the corresponding hp_en_ bit (r44h[3:0], table 38) to 1. by default, if auto = 1, the hp_en_ bits will be set to 1 automatically after a reset event. when enabled, each port?s high-power settings can be indi- vidually configured using the corresponding port gpmd, port overcurrent (icut), port current-limit (ilim_), and port high-power status registers (see the register map and description section, tables 39?42). figure 2. detection, 2-event classification, and port power-up sequence v out_ - v agnd 150ms 150ms 19ms 19ms 9ms 9ms t det(1) t det(2) t class(1) t class(2) t -54v -18v -9.1v -4v 0v 80ms downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 20 foldback current during startup and normal operation, an internal cir- cuit senses the voltage at out_ and when necessary reduces the current-limit clamp voltage (v su_lim ) to help reduce the power dissipation through the external fet. when i lim_ = 80h (classes 0?3), foldback begins when v out_ - v ee > 32v; and when i lim_ = c0h (classes 4 and 5), foldback begins when v out_ - v ee > 18v. the v su_lim eventually reduces down to the mini- mum current-limit threshold (v th_fb = 35mv) when v out_ - v ee > 46v (figure 3). mosfet gate driver connect the gate of the external n-channel mosfet to gate_. an internal 50 f a current source pulls gate_ to (v ee + 10v) to turn on the mosfet. an internal 40 f a current source pulls down gate_ to v ee to turn off the mosfet. the pullup and pulldown current controls the maximum slew rate at the output during turn-on or turn-off. use the following equation to set the maximum slew rate: out_ gate_ gd v i t c ? = ? where c gd is the total capacitance between the gate and the drain of the external mosfet. the current limit and the capacitive load at the drain control the slew rate during startup. during current-limit regulation, the device manipulates the gate_ voltage to control the voltage at sense_ (v rsense_ ). a fast pulldown activates if v rsense_ overshoots the limit threshold (v su_lim ). the fast pulldown current increases with the amount of over- shoot, and the maximum fast pulldown current is 50ma. during turn-off, when the gate_ voltage reaches a value lower than 1.2v, a strong pulldown switch is activated to keep the mosfet securely off. interrupt the device contains an open-drain logic output ( int ) that goes low when an interrupt condition exists. the in terrupt register (r00h, table 6) contains the interrupt fla g bits and the interrupt mask register (r01h, table 7) determi nes which events can trigger an interrupt. when an even t occurs, the appropriate interrupt event register bi ts (in r02h to r0bh) and the corresponding interrupt (in r 00h) are set to 1 and int is asserted low (unless masked). if the master device on the i 2 c bus sends out an alert response address, any max5980 device on the bus tha t has int asserted will respond (see the global addressing and the alert response address (ara) section). as a response to an interrupt, the controller can read the status of the event register(s) to determine the cause of the interrupt and take appropriate action. each inter- rupt event register is paired with a clear-on-read (cor) register. when an interrupt event register is read through the corresponding cor register, the corresponding event register is reset to 0 (clearing that interrupt event). int remains low and the interrupt is not reset when the interrupt event register is read through the read-only address. for example, to clear a supply event fault read r0bh (cor) not r0ah (read-only, see table 12). use the int_clr bit (r1ah[7], table 27) to clear an interrupt, or the reset_ic bit (r1ah[4]) to initiate software resets. figure 3. foldback current characteristics v out_ - v ee v th_fb 35mv v sense_ - v ee v su_lim 212.5mv v su_lim 106.25mv class 0 ?3 class 4 v flbk_st 18v v flbk_end 46v v flbk_st 32v downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 21 undervoltage and overvoltage protection the device contains undervoltage and overvoltage pro- tection features, and the flag bits can be found in the supply event register (r0ah and r0bh, table 12) and the watchdog register (r42h, table 36). an internal v ee undervoltage lockout circuit keeps the mosfet off and the device in reset until v agnd - v ee exceeds 28.5v for more than 3ms. an internal v ee overvoltage circuit shuts down the ports when v agnd - v ee exceeds 62.5v. the digital supply also contains an undervoltage lockout that triggers when v dd - v ee p 2v. dc disconnect monitoring the dc disconnect monitoring settings are found in the disconnect enable register (r13h, table 21). to ena ble dc disconnect, set either the acd_en_ or dcd_en_ bi t for the corresponding port to 1. to disable the dc discon- nect monitoring, both the acd_en_ and dcd_en_ bit f or that port must be set to 0. when enabled, if v rsense_ (the voltage across r sense_ ) falls below the dc load disconnect threshold, v dcth , for more than t disc , the device turns off power and asserts the dis_ bit for the corresponding port (r06h[7:4] and r07h[7:4], table 10). v dd power supply the device has an internally regulated, 3.3v digital sup- ply that powers the internal logic circuitry. v dd has an undervoltage lockout (v dd_uvlo ) of 2v, and an under- voltage condition on v dd keeps the device in reset and the ports shut off. when v dd has recovered and the reset condition clears, the vdd_uvlo bit in the supply event registers is set to 1 (r0ah[5] and r0bh[5], table 12). the digital address inputs, auto, and midspan are internally pulled up to v dd , and all digital inputs are referenced to dgnd. v dd can also be used to source up to 10ma for external circuitry. for internal regulator stability, connect a 1.8k i resistor in parallel with a 33nf capacitor at the v dd output (figure 4). if an external load is to be shared among multiple max5980 devices, isolate the external supply bus with a series resistor (50 i for 3 devices, 75 i for 4 devices), and place a single 1 f f capacitor on the bus. hardware power-down the en digital input is referenced to dgnd and is used for hardware level control of device power management. during normal operation, en should be externally pulled directly up to v dd , the 3.3v internal regulator output (see the typical operating circuit ). to initiate a hardware reset and port power-down, pull en to dgnd for at least 100 f s. while en is held low, the device remains in reset and the ports remain securely powered down. normal device operation resumes once en is pulled up to the v dd . thermal shutdown if the device's die temperature reaches +140 n c (typ), an overtemperature fault is generated and the device shuts down. the die temperature must cool down below +120 n c (typ) to remove the overtemperature fault con- dition. after a thermal shutdown condition clears, the device is reset and the tsd event bit is set to a logical 1 (r0ah[7]/r0bh[7], table 12). watchdog the watchdog register (r42h, table 36) is used to monitor device status, and to enable and monitor th e watchdog functionality. on a power-up or after a re set condition, this register is set to a default value of 16h. wd_dis[3:0] is set by default to 1011, disabling th e watchdog timeout. set wd_dis[3:0] to any other valu e to enable the watchdog. the watchdog monitors the scl line for activity. if there are no transitions for 2.5s (typ), the wd_stat bit is set to 1 and all ports ar e pow- ered down (using the individual port reset protocol ). wd_stat must be reset before any port can be reenab led. figure 4. v dd external power sourcing max5980 v dd external3.3v bus r isolation i external p 10ma externalbus gnd 1.8k i 33nf 1f dgnd downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 22 device address (ad0) the max5980 is programmable to 1 of 16 unique slave device addresses. the three msbs of the device address are always [010]. the 4 lsbs of the device address are programmable, and are formed by the states of the slave address inputs (a0, a1, a2, and a3; see table 3). to program the device address, connect a0, a1, a2, and a3 to a combination of v dd (logical 1) and dgnd (logi- cal 0), and initiate a device reset. i 2 c-compatible serial interface the device operates as a slave that sends and receives data through an i 2 c-compatible, 2-wire or 3-wire inter- face. the interface uses a serial-data input line (sdain), a serial-data output line (sdaout), and a serial-clock line (scl) to achieve bidirectional communication between master(s) and slave(s). a master (typically a microcon- troller) initiates all data transfers to and from the device, and generates the scl clock that synchronizes the data transfer. in most applications, connect the sdain and the sdaout lines together to form the serial-data line (sda). most of the figures shown label the bus as sda. using the separate input and output data lines allows optocoupling with the controller bus when an isolated supply powers the microcontroller. the device's sdain line operates as an input and sdaout operates as an open-drain output. a pullup resistor, typically 4.7k i , is required on sdaout (3-wire mode) or sda (2-wire mode). the scl line operates only as an input. a pullup resistor, typically 4.7k i , is required on scl if there are multiple masters, or if the master in a single-master system has an open-drain scl output. serial addressing each transmission consists of a start condition sent by a master, followed by the device's 7-bit slave address plus r/w bit, a register address byte, 1 or more data bytes, and finally a stop condition. table 3. programmable device address settings figure 5. serial interface timing details scl sda/sdain t low t high t r t f t buf start condition stop condition repeated start condition start condition t hd, sta t su, dat t hd, dat t su, sta t hd, sta t su, sto device address b7 b6 b5 b4 b3 b2 b1 0 1 0 a3 a2 a1 a0 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 23 start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high. when the master finishes communicating with the slave, the master issues a stop (p) condition by transitioning sda from low to high while scl is high. the stop condition frees the bus for anoth- er transmission (see figure 6). bit transfer each clock pulse transfers one data bit (figure 7). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit (figure 8) that the recipient uses to handshake receipt of each byte of data. thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, so the sda line is stable low during the high period of the clock pulse. when the master transmits to the max5980, the device generates the acknowledge bit. when the device transmits to the master, the master generates the acknowledge bit. figure 6. start and stop conditions figure 7. bit transfer figure 8. acknowledge start stop s p sda/ sdain scl sda/sdain scl data line stable; data valid change of data allowed scl sda/sdain by transmitter clock pulse for acknowledgment start condition sda/sdaout by receiver 1 2 8 9 s downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 24 slave address the device has a 7-bit long slave address (figure 9). the bit following the 7-bit slave address (bit eight) is the r/ w bit, which is low for a write command and high for a read command. the upper five bits of the slave address can- not be changed and are always [01000]. using the ad0 input, the lowest two bits can be programmed to assign the device one of four unique slave addresses (see table 3). the device monitors the bus continuously, wait- ing for a start condition followed by the device?s slave address. when a device recognizes its slave address, it acknowledges and is then ready for continued com- munication. global addressing and the alert reponse address (ara) the global address call is used in write mode to wr ite to the same register to multiple devices (address 60h) . the global address call can also be used in read mode ( 61h) in the same way as the alert response address (ara) . the actual alert response address (ara) is 0ch. the max5980 slave device only responds to the ara if it s int (interrupt) output is asserted. all max5980 device s in which the int output is not asserted ignore the ara. when responding to the ara, the device transmits a byte of data on sdaout containing its own address in the top 7 bits, and a 1 in the lsb (as does every other device connected to the sdain line that has an active interrupt). as each bit in the byte is transmitted, the device determines whether to continue transmitting the remainder of the byte or terminate transmission. the device terminates the transmission if it sees a 0 on sda at a time when it is attempting to send a 1; otherwise it continues transmitting bits until the entire byte has been sent. this litigation protocol always allows the part with the lowest address to complete the transmission, and the microcontroller can respond to that interrupt. the device deasserts int if it completes the transmission of the entire byte. if the device did not have the lowest address, and terminates the transmission early, the int output remains asserted. in this way, the microcontroller can continue to send ara read cycles until all slave devices successfully transmit their addresses, and all interrupt requests are resolved. general call in compliance with the i 2 c specification, the device responds to the general call through global address 30h. message format for writing to the max5980 a write to the device comprises the device slave address transmission with the r w bit set to 0, followed by at least 1 byte of information. the first byte of information is the command byte (figure 10). the command byte determines which register of the device is written to by the next byte, if received. if the device detects a stop condition after receiving the command byte but before receiving any data, then the device takes no further action beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the device selected by the command byte (figure 11). the control byte address then autoincrements (if pos- sible; see table 4) and then waits for the next data byte or a stop condition. if multiple data bytes are transmitted before a stop con- dition is detected, these bytes are stored in subsequent max5980 internal registers as the control byte address autoincrements (figure 12). if the control byte address can no longer increment, any subsequent data sent con- tinues to write to that address. figure 9. slave address figure 10. write format, control byte received scl msb sda/ sdain 1 0 lsb 0 a3 a2 a1 a0 r/w ack r/w cb7 s 0 p ack ack cb6 cb5 cb4 cb3 cb2 cb1 cb0 control byte stored on stop condition acknowledge from the max5980 slave address control byte acknowledge from the max5980 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 25 message format for reading a read command for the device comprises the device slave address transmission with the r/ w bit set to 1, fol- lowed by at least 1 byte of information. as with a write command, the first byte of information is the command byte. the device then reads using the internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. this pointer autoincrements after reading each data byte using the same rules as for a write, though the master now sends the acknowledge bit after each read receipt (figure 13). when performing read-after-write verification, remember to reset the command byte?s address because the stored control byte address auto- increments after the write. figure 11. write format, control, and single data byte written figure 12. write format, control, and n data bytes written figure 13. read format, control, and n data bytes read r/w cb7 s 0 ack ack ack p cb6 cb5 cb4 cb3 cb2 cb1 cb0 d7 d6 d5 d4 d3 d2 d1 d0 control byte stored on stop condition acknowledge from the max5980 slave address control byte data byte (1 byte) word address autoincrement acknowledge from the max5980 s 0 ack ack ack p slave address control byte data byte (n bytes) cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 control byte stored on stop condition acknowledge from the max5980 r/w d7 d6 d5 d4 d3 d2 d1 d0 word address autoincrement repeat for n bytes acknowledge from the max5980 s 1 ack ack ack/ nack slave address control byte data byte (n bytes) cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 control byte stored on stop condition acknowledge from the max5980 r/w d7 d6 d5 d4 d3 d2 d1 d0 acknowledge/nack from the master acknowledge from the max5980 word address autoincrement repeat for n bytes (ack) p (nack) downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 26 operation with multiple masters when the device operates on a 3-wire interface with mul- tiple masters, a master reading the device should use repeated starts between the write that sets the device?s address pointer, and the read(s) that take the data from the location(s). it is possible for master 2 to take over the bus after master 1 has set up the device?s address pointer but before master 1 has read the data. if master 2 subsequently resets the device?s address pointer, then master 1?s read may be from an unexpected location. command address autoincrementing address autoincrementing allows the device to be con- figured with fewer transmissions by minimizing the num- ber of times the command address needs to be sent. the command address stored in the device generally increments after each data byte is written or read (table 4). the device is designed to prevent overwrites on unavailable register addresses and unintentional wrap- around of addresses. table 4. autoincrement rules table 5. register map summary command byte address range autoincrement behavior 0x00 to 0x71 command address autoincrements after byte read or written 0x71 command address remains at 0x71 after byte written or read addr register name type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state interrupts 00h interrupt r sup_int tst_int tcut_int cls_int det_int dis_int pg_int pe_int 1000?0000 01h interrupt mask r/w sup_mask tst_mask tcut_mask cls_mask det_mask dis_mask pg_mask pe_mask 1xx0?0x00 events 02h power event r pg_chg4 pg_chg3 pg_chg2 pg_chg1 pe_chg4 pe_chg3 pe_chg2 pe_chg1 0000?0000 03h power event cor cor 04h detect event r cls4 cls3 cls2 cls1 det4 det3 det2 det1 0000?0000 05h detect event cor cor 06h fault event r dis4 dis3 dis2 dis1 tcut4 tcut3 tcut2 tcut1 0000?0000 07h fault event cor cor 08h startup event r icv4 icv3 icv2 icv1 tstart4 tstart3 tstart2 tstart1 0000?0000 09h startup event cor cor 0ah supply event r tsd fetbad v dd_uvlo v ee_uvlo ? ? ? ? 0000?0010 0bh supply event cor cor downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 27 table 5. register map summary (continued) addr register name type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state status 0ch port 1 status r ? class1[2] class1[1] class1[0] ? det_st1[2] det_st1[1] det_st1[0] 0000?0000 0dh port 2 status r ? class2[2] class2[1] class2[0] ? det_st2[2] det_st2[1] det_st2[0] 0000?0000 0eh port 3 status r ? class3[2] class3[1] class3[0] ? det_st3[2] det_st3[1] det_st3[0] 0000?0000 0fh port 4 status r ? class4[2] class4[1] class4[0] ? det_st4[2] det_st4[1] det_st4[0] 0000?0000 10h power status r pgood4 pgood3 pgood2 pgood1 pwr_en4 pwr_en3 pwr_en2 pwr_en1 0000?0000 11h pin status r ? ? slave[1] slave[0] id[1] id[0] ? auto 00xx?xx0x configuration 12h operating mode r/w p4_m[1] p4_m[0] p3_m[1] p3_m[0] p2_m[1] p2_m[0] p1_m[1] p1_m[0] xxxx?xxxx 13h disconnect enable r/w acd_en4 acd_en3 acd_en2 acd_en1 dcd_en4 dcd_en3 dcd_en2 dcd_en1 xxxx?0000 14h detection and classification enable r/w class_en4 class_en3 class_en2 class_en1 det_en4 det_en3 det_en2 det_en1 xxxx?xxxx 15h midspan enable r/w ? ? ? ? midspan4 midspan3 midspan2 midspan1 0000?xxxx 16h reserved r/w ? ? ? ? ? ? ? ? ? 17h miscellaneous configuration 1 r/w int_en det_chg ? ? ? ? ? ? 1010?0000 pushbuttons 18h detection/ classification pushbutton w cls_pb4 cls_pb3 cls_pb2 cls_pb1 det_pb4 det_pb3 det_pb2 det_pb1 0000?0000 19h power-enable pushbutton w pwr_off4 pwr_off3 pwr_off2 pwr_off1 pwr_on4 pwr_on3 pwr_on2 pwr_on1 0000?0000 1ah global pushbutton w int_clr pin_clr ? reset_ic reset_p4 reset_p3 reset_p2 reset_p1 0000?0000 general 1bh id r id_code[4] id_code[3] id_code[2] id_code[1] id_code[0] rev[2] rev[1] rev[0] 1101?0000 1ch class 5 enable r/w ? ? ? ? cl5_en4 cl5_en3 cl5_en2 cl5_en1 0000?0000 1dh reserved ? ? ? ? ? ? ? ? ? ? 1eh tlim1/2 programming r/w tlim2[3] tlim2[2] tlim2[1] tlim2[0] tlim1[3] tlim1[2] tlim1[1] tlim1[0] 0000?0000 1fh tlim3/4 programming r/w tlim4[3] tlim4[2] tlim4[1] tlim4[0] tlim3[3] tlim3[2] tlim3[1] tlim3[0] 0000?0000 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 28 table 5. register map summary (continued) addr register name type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state maxim reserved 20h reserved ? ? ? ? ? ? ? ? ? ? 21h reserved ? ? ? ? ? ? ? ? ? ? 22h reserved ? ? ? ? ? ? ? ? ? ? 23h reserved ? ? ? ? ? ? ? ? ? ? 24h reserved ? ? ? ? ? ? ? ? ? ? 25h reserved ? ? ? ? ? ? ? ? ? ? 26h reserved ? ? ? ? ? ? ? ? ? ? 27h reserved ? ? ? ? ? ? ? ? ? ? 28h reserved ? ? ? ? ? ? ? ? ? ? 29h miscellaneous configuration 2 r/w ? ? ? lsc_en vee_r4 vee_r3 vee_r2 vee_r1 0000?0000 2ah reserved ? ? ? ? ? ? ? ? ? ? 2bh reserved ? ? ? ? ? ? ? ? ? ? 2ch reserved ? ? ? ? ? ? ? ? ? ? 2dh reserved ? ? ? ? ? ? ? ? ? ? 2eh reserved ? ? ? ? ? ? ? ? ? ? 2fh reserved ? ? ? ? ? ? ? ? ? ? current/voltage 30h port 1 current r ip1[7] ip1[6] ip1[5] ip1[4] ip1[3] ip1[2] ip1[1] ip1[0] 0000?0000 31h port 1 current r ip1[15] ip1[14] ip1[13] ip1[12] ip1[11] ip1[10] ip1[9] ip1[8] 0000?0000 32h port 1 voltage r vp1[7] vp1[6] vp1[5] vp1[4] vp1[3] vp1[2] vp1[1] vp1[0] 0000?0000 33h port 1 voltage r vp1[15] vp1[14] vp1[13] vp1[12] vp1[11] vp1[10] vp1[9] vp1[8] 0000?0000 34h port 2 current r ip2[7] ip2[6] ip2[5] ip2[4] ip2[3] ip2[2] ip2[1] ip2[0] 0000?0000 35h port 2 current r ip2[15] ip2[14] ip2[13] ip2[12] ip2[11] ip2[10] ip2[9] ip2[8] 0000?0000 36h port 2 voltage r vp2[7] vp2[6] vp2[5] vp2[4] vp2[3] vp2[2] vp2[1] vp2[0] 0000?0000 37h port 2 voltage r vp2[15] vp2[14] vp2[13] vp2[12] vp2[11] vp2[10] vp2[9] vp2[8] 0000?0000 38h port 3 current r ip3[7] ip3[6] ip3[5] ip3[4] ip3[3] ip3[2] ip3[1] ip3[0] 0000?0000 39h port 3 current r ip3[15] ip3[14] ip3[13] ip3[12] ip3[11] ip3[10] ip3[9] ip3[8] 0000?0000 3ah port 3 voltage r vp3[7] vp3[6] vp3[5] vp3[4] vp3[3] vp3[2] vp3[1] vp3[0] 0000?0000 3bh port 3 voltage r vp3[15] vp3[14] vp3[13] vp3[12] vp3[11] vp3[10] vp3[9] vp3[8] 0000?0000 3ch port 4 current r ip4[7] ip4[6] ip4[5] ip4[4] ip4[3] ip4[2] ip4[1] ip4[0] 0000?0000 3dh port 4 current r ip4[15] ip4[14] ip4[13] ip4[12] ip4[11] ip4[10] ip4[9] ip4[8] 0000?0000 3eh port 4 voltage r vp4[7] vp4[6] vp4[5] vp4[4] vp4[3] vp4[2] vp4[1] vp4[0] 0000?0000 3fh port 4 voltage r vp4[15] vp4[14] vp4[13] vp4[12] vp4[11] vp4[10] vp4[9] vp4[8] 0000?0000 other functions 40h reserved ? ? ? ? ? ? ? ? ? ? 41h firmware r/w 0 0 0 0 0 0 0 0 0000?0000 42h watchdog r ? vee_ov vee_uv wd_dis[3] wd_dis[2] wd_dis[1] wd_dis[0] wd_stat 0001?0110 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 29 table 5. register map summary (continued) x indicates that the register reset state depends on either the status of the external programming pins (a3?a0, en_cl5, auto, and midspan) or that the cause of the reset condition determines the state. ? indicates that the register is either unused or reserved. always write a logic-low to any reserved bits when programming a reg- ister, unless otherwise indicated in the register map and description section. addr register name type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state 43h developer id/revision number r/w dev_id[2] dev_id[1] dev_id[0] ? ? dev_rev[2] dev_rev[1] dev_rev[0] 0000?0000 44h high-power enable r/w ? ? ? ? hp_en4 hp_en3 hp_en2 hp_en1 0000?xxxx 45h reserved ?- ? ? ? ? ? ? ? ? ? 46h port 1 gpmd r/w ? ? ? ? ? ? leg_en1 pong_en1 0000?000x 47h port 1 icut r/w rdis1 cut_rng1 icut1[5] icut1[4] icut1[3] icut1[2] icut1[1] icut1[0] xx01?0100 48h port 1 ilim r/w 1 ilim1 0 0 0 0 0 0 1000?0000 49h port 1 high- power status r ? ? ? ? ? ? fet_bad1 pong_pd1 0000?0000 4ah reserved ? ? ? ? ? ? ? ? ? ? 4bh port 2 gpmd r/w ? ? ? ? ? ? leg_en2 pong_en2 0000?000x 4ch port 2 icut r/w rdis2 cut_rng2 icut2[5] icut2[4] icut2[3] icut2[2] icut2[1] icut2[0] xx01?0100 4dh port 2 ilim r/w 1 ilim2 0 0 0 0 0 0 1000?0000 4eh port 2 high- power status r ? ? ? ? ? ? fet_bad2 pong_pd2 0000?0000 4fh reserved ? ? ? ? ? ? ? ? ? ? 50h port 3 gpmd r/w ? ? ? ? ? ? leg_en3 pong_en3 0000?000x 51h port 3 icut r/w rdis3 cut_rng3 icut3[5] icut3[4] icut3[3] icut3[2] icut3[1] icut3[0] xx01?0100 52h port 3 ilim r/w 1 ilim3 0 0 0 0 0 0 1000?0000 53h port 3 high- power status r ? ? ? ? ? ? fet_bad3 pong_pd3 0000?0000 54h reserved ? ? ? ? ? ? ? ? ? ? 55h port 4 gpmd r/w ? ? ? ? ? ? leg_en4 pong_en4 0000?000x 56h port 4 icut r/w rdis4 cut_rng4 icut4[5] icut4[4] icut4[3] icut4[2] icut4[1] icut4[0] xx01?0100 57h port 4 ilim r/w 1 ilim4 0 0 0 0 0 0 1000?0000 58h port 4 high- power status r ? ? ? ? ? ? fet_bad4 pong_pd4 0000?0000 59h reserved ? ? ? ? ? ? ? ? ? ? 5ah reserved ? ? ? ? ? ? ? ? ? ? 5bh reserved ? ? ? ? ? ? ? ? ? ? 5ch reserved ? ? ? ? ? ? ? ? ? ? 5dh reserved ? ? ? ? ? ? ? ? ? ? 5eh reserved ? ? ? ? ? ? ? ? ? ? 5fh reserved ? ? ? ? ? ? ? ? ? ? downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 30 register map and description the device contains a bank of volatile registers that store its settings and status. the device features an i 2 c- compatible, 3-wire serial interface, allowing the registers to be fully software configurable and programmable. in addition, several registers are also pin-programmable to allow the device to operate in auto mode and still be partially configurable even without the assistance of software. interrupt registers (r00h, r01h) interrupt register (r00h) the interrupt register (r00h, table 6) summarizes the event register status and is used to send an interrupt signal to the controller. on power-up or after a reset condition, interrupt (r00h) is set to a default value of 00h (it may almost immediately report an interrupt depend- ing on if it was a power-up or reset condition, and in the case of reset the type/cause of reset). int goes low to report an interrupt event if any one of the active interrupt bits is set to 1 (active-high) and it is not masked by the interrupt mask register (r01h, table 7). int does not go low to report an interrupt if the corresponding mask bit (r01h) is set. writing a 1 to int_clr (r1ah[7], table 27) clears all interrupt and events registers (resets to low). int_en (r17h[7], table 24) is a global interrupt enable and writing a 0 to int_en disables the int output, put- ting it into a state of high impedance. table 6. interrupt register address = 00h description symbol bit no. type sup_int 7 r interrupt signal for supply faults. sup_int is the logic or of all the active bits in the supply event register (r0ah/r0bh[7:4], table 12). tst_int 6 r interrupt signal for startup failures. tst_int is the logic or of the tstart_ bits in the startup event register (r08h/r09h[3:0], table 11). tcut_int 5 r interrupt signal for port overcurrent and current-limit violations. tcut_int is the logic or of the tcut_ bits in the fault event register (r06h/r07h, table 10) and the icv_ bits in the startup event register (r08h/r09h, table 11). cls_int 4 r interrupt signal for completion of classification. cls_int is the logic or of the cls_ bits in the detect event register (r04h/r05h, table 9). det_int 3 r interrupt signal for completion of detection. det_int is the logic or of the det_ bits in the detect event register (r04h/r05h, table 9). dis_int 2 r interrupt signal for a dc load disconnect. dis_int is the logic or of the dis_ bits in the fault event register (r06h/r07h, table 10). pg_int 1 r interrupt signal for pgood_ (r10h[7:4]) status changes. pg_int is the logic or of the pg_chg_ bits in the power event register (r02h/r03h, table 8). pe_int 0 r interrupt signal for power enable status change. pe_int is the logic or of the pe_chg_ bits in the power event register (r02h/r03h, table 8). downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 31 interrupt mask register (r01h) the interrupt mask register (r01h, table 7) contains mask bits that suppress the corresponding interrupt bits in register r00h (active-high). setting mask bits low individually disables the corresponding interrupt signal. when masked (set low), the corresponding bits are still set in the interrupt register (r00h) but the masking bit (r01h) suppresses the generation of an interrupt signal ( int ). supply interrupts set on a power-up or reset event cannot be masked, such as tsd, v dd_uvlo , and v ee_ uvlo . on power-up or a reset condition, the interrupt mask register is set to a default state of e4h if auto is high, and 80h is auto is low. event registers (r02h?r08h) power event register (r02h/r03h) the power event register (r02h/r03h, table 8) records changes in the power status of the port. on power- up or after a reset condition, the power event reg- ister is set to a default value of 00h. any change in pgood_ (r10h[7:4]) sets pg_chg_ to 1. any change in pwr_en_ (r10h[3:0]) sets pe_chg_ to 1. pg_chg_ and pe_chg_ trigger on the transition edges of pgood_ and pwr_en_, and do not depend on the actual logic status of the bits. the power event register has two addresses. when read through the r02h address, the content of the register is left unchanged. when read through the clear on read (cor) r03h address, the register content is reset to the default state. table 7. interrupt mask register table 8. power event register address = 01h description symbol bit no. type sup_mask 7 r/w supply interrupt mask. a logic-high enables the sup_int interrupt. a logic-low disables the sup_int interrupts. tst_mask 6 r/w startup interrupt mask. a logic-high enables the tst_int interrupt. a logic-low disables the tst_int interrupts. tcut_mask 5 r/w current interrupt mask. a logic-high enables the tcut_int interrupt. a logic-low disables the tcut_int interrupt. cls_mask 4 r/w classification interrupt mask. a logic-high enables the cls_int interrupt. a logic-low disables the cls_end interrupt. det_mask 3 r/w detection interrupt mask. a logic-high enables the det_int interrupt. a logic-low disables the det_int interrupt. dis_mask 2 r/w dc disconnect interrupt mask. a logic-high enables the dis_int interrupts. a logic-low disables the dis_int interrupts. pg_mask 1 r/w pgood interrupt mask. a logic-high enables the pg_int interrupts. a logic-low disables the pg_int interrupts. pe_mask 0 r/w power-enable interrupt mask. a logic-high enables the pe_int interrupts. a logic-low disables the pe_int interrupts. address = 02h 03h description symbol bit no. type type pg_chg4 7 r cor pgood change event for port 4 pg_chg3 6 r cor pgood change event for port 3 pg_chg2 5 r cor pgood change event for port 2 pg_chg1 4 r cor pgood change event for port 1 pe_chg4 3 r cor power enable change event for port 4 pe_chg3 2 r cor power enable change event for port 3 pe_chg2 1 r cor power enable change event for port 2 pe_chg1 0 r cor power enable change event for port 1 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 32 detect event register (r04h/r05h) the detect event register (r04h/r05h, table 9) records detection/classification events for the port. on power-up or after a reset condition, the detect event register is set to a default value of 00h. det_ and cls_ are set high whenever detection/classification is completed on the corresponding port. as with the other event registers, the detect event register has two addresses. when read through the r04h address, the content of the register is left unchanged. when read through the cor r05h address, the register content is reset to the default state. fault event register (r06h/r07h) the fault event register (r06h/r07h, table 10) records port dc load and overcurrent disconnect timeout events. on power-up or after a reset condition, the fault event register is set to a default value of 00h. dis_ is set to 1 whenever a port shuts down due to a dc load discon- nect event. tcut_ is set to 1 when a port shuts down due to an extended overcurrent event after a success- ful startup. as with the other events registers, the fault event register has two addresses. when read through the r06h address, the content of the register is left unchanged. when read through the cor r07h address, the register content is reset to the default state. table 9. detect event register table 10. fault event register address = 04h 05h description symbol bit no. type type cls4 7 r cor classification completed on port 4 cls3 6 r cor classification completed on port 3 cls2 5 r cor classification completed on port 2 cls1 4 r cor classification completed on port 1 det4 3 r cor detection completed on port 4 det3 2 r cor detection completed on port 3 det2 1 r cor detection completed on port 2 det1 0 r cor detection completed on port 1 address = 06h 07h description symbol bit no. type type dis4 7 r cor dc load disconnect timeout on port 4 dis3 6 r cor dc load disconnect timeout on port 3 dis2 5 r cor dc load disconnect timeout on port 2 dis1 4 r cor dc load disconnect timeout on port 1 tcut4 3 r cor overcurrent disconnect timeout on port 4 tcut3 2 r cor overcurrent disconnect timeout on port 3 tcut2 1 r cor overcurrent disconnect timeout on port 2 tcut1 0 r cor overcurrent disconnect timeout on port 1 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 33 startup event register (r08h/r09h) the startup event register (r08h/r09h, table 11) re cords port startup failure events and current-limit disco nnect timeout events. on power-up or after a reset condit ion, the fault event register is set to a default value of 0 0h. icv_ is set to 1 when a port shuts down due to an extended cur- rent-limit event after startup. tstart is set to 1 whenever a port fails startup due to an overcurrent or curre nt-limit event during startup. as with the other event regis ters, the startup event register has two addresses. when read through the r08h address, the content of the regist er is left unchanged. when read through the cor r09h address, the register content is reset to the defau lt state. supply event register (r0ah/r0bh) the device monitors die temperature, external fet sta- tus, and the analog and digital power supplies, and sets the appropriate bits in the supply event register (r0ah/ r0bh, table 12). on power-up or after a reset condition, the supply event register is set to a default value of 02h (but may immediately change depending on the cause of the reset). a thermal-shutdown circuit monitors the temperature of the die and resets the device if the temperature exceeds +140 n c. tsd is set to 1 after the device recovers from thermal shutdown and returns to normal operation. if a fet failure is detected on one or more ports, fetbad is set high. to determine which port the failure was detected on, check the fet_bad_ bit in the hp status register of each port (table 42). fet_bad_ is set to 1 if the port is powered, there is no current-limit condition, and v out_ - v ee > 2v. when v ee or v dd are below their uvlo thresholds, the device is in reset mode and securely holds the port off. when they rise above the uvlo threshold, the device comes out of reset and the appropriate v dd_uvlo / v ee_uvlo bit in the supply event register is set to 1. table 11. startup event register table 12. supply event register address = 08h 09h description symbol bit no. type type icv4 7 r cor current-limit disconnect timeout on port 4 icv3 6 r cor current-limit disconnect timeout on port 3 icv2 5 r cor current-limit disconnect timeout on port 2 icv1 4 r cor current-limit disconnect timeout on port 1 tstart4 3 r cor startup failure on port 4 tstart3 2 r cor startup failure on port 3 tstart2 1 r cor startup failure on port 2 tstart1 0 r cor startup failure on port 1 address = 0ah 0bh description symbol bit no. type type tsd 7 r cor overtemperature shutdown fetbad 6 r cor fetbad is set if a fet failure is detected on one or more ports v dd_uvlo 5 r cor v dd undervoltage-lockout condition v ee_uvlo 4 r cor v ee undervoltage-lockout condition reserved 3 r cor reserved reserved 2 r cor reserved reserved 1 r cor reserved reserved 0 r cor reserved downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 34 status registers (r0ch?r11h) port status registers (r0ch?r0fh) the port status registers (r0ch?r0fh, table 13) record the results of the port detection and classification at the end of each phase in three encoded bits. on power- up or after a reset condition, the port status register is set to a default value of 00h. tables 14 and 15 are the detection and classification result decoding tables respectively. for leg_en = 0 (port gpmd register, table 39), the detection result is shown in table 13. when clc_en = 1, the device allows valid detection of high capacitive loads of up to 100 f f (typ), and reports the result as high_cap. if cl5_en_ = 1, any classification current in excess of class 4 but less than the classifica- tion current limit will return a class 5 classification result. if cl5_en_ = 0, any classification current in excess of class 4 will return a current-limit classification result, and the port will not power up. table 13. port status register table 14. detection result decoding chart table 15. classification result decoding chart address = 0ch, 0dh, 0eh, 0fh description symbol bit no. type reserved 7 ? reserved class_[2:0] 6 r classification result for the corresponding port (table 14) 5 r 4 r reserved 3 ? reserved det_st_[2:0] 2 r detection result for the corresponding port (table 13) 1 r 0 r det_st_[2:0] detected description 000 none detection status unknown (default) 001 dcp positive dc supply connected at the port (v agnd - v out_ < 1v) 010 high cap high capacitance at the port (> 8.5 f f (typ)) 011 rlow low resistance at the port (r det < 15k i ) 100 det_ok detection pass (15k i > r det > 33k i ) 101 rhigh high resistance at the port (r det > 33k i ) 110 open open port (i out_ < 10 f a) 111 dcn low impedance to v ee at the port (v out_ - v ee < 2v) class_[2:0] class result 000 unknown 001 1 010 2 011 3 100 4 101 5 110 0 111 current limit downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 35 power status register (r10h) the power status register (r10h, table 16) records the current status of port power. on power-up or after a reset condition, the port is initially unpowered and the power status register is set to its default value of 00h. pgood_ (r10h[7:4]) is set to 1 at the end of the power-up startup period if v out_ - v ee > pg th for more than t pgood . pgood_ is a real-time bit and is reset to 0 whenever v out_ - v ee p pg th , or a fault condition occurs. pwr_en_ (r10h[3:0]) is set to 1 when the port power is turned on. pwr_en resets to 0 as soon as the port turns off. any transition of pgood_ and pwr_en_ bits set the corresponding bit in the power event register (r02h/r03h, table 8). pin status register (r11h) the pin status register (r11h, table 17) records th e state of the a3, a2, a1, a0, and auto pins. the states of a3 and a2 (into id[1:0]), a1 and a0 (into slave[1:0]), and auto are latched into their corresponding bits afte r a power-up or reset condition clears. therefore, the default state of the pin status register depends on those i nputs (00xx?xx0x). changes to those inputs during normal operation are ignored and do not change the registe r contents. a3, a2, a1, and a0 all have internal pull ups, and when left unconnected result in a default addre ss of 0101111 (2fh). connect one or more low before a pow er- up or device reset to reprogram the slave address. slave[1:0] also typically indicates which of the 16 pse-icm ports the slave device controls (table 18). table 16. power status register table 17. pin status register table 18. pse-icm port control mapping address = 10h description symbol bit no. type pgood4 7 r power-good condition on port 4 pgood3 6 r power-good condition on port 3 pgood2 5 r power-good condition on port 2 pgood1 4 r power-good condition on port 1 pwr_en4 3 r power is enabled on port 4 pwr_en3 2 r power is enabled on port 3 pwr_en2 1 r power is enabled on port 2 pwr_en1 0 r power is enabled on port 1 address = 11h description symbol bit no. type reserved 7 ? reserved reserved 6 ? reserved slave[1:0] 5 r slave input (a1 and a0) latched-in status (table 3) 4 r id[1:0] 3 r id input (a3 and a2) latched-in status (table 3) 2 r reserved 1 ? reserved auto 0 r auto input latched-in status slave[1:0] pse-icm ports controlled 00 slave device controls ports a, b, c, and d 01 slave device controls ports e, f, g, and h 10 slave device controls ports i, j, k, and l 11 slave device controls ports m, n, o, and p downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 36 configuration registers (r12h?r17h) operating mode register (r12h) the operating mode register in the device (r12h, table 19) contains 2 bits per port that set the port mode of operation. table 20 details how to set the mode of operation for the device. on a power-up or after a reset condition, if auto = 1, the operating mode register is set to a default value of ffh. if auto = 0, the operating mode register is set to 00h. use software to program the mode of operation. the software port specific reset using reset_p_ (r1ah[3:0]), table 27) does not affect the mode register. disconnect enable register (r13h) the disconnect enable register (r13h, table 21) is used to enable dc load disconnect detection. on power-up or after a reset condition, if auto = 1, this register is reset to a default value of f0h. if auto = 0, it is set to 00h. setting either acd_en_ (r13h[7:4]) or dcd_en _ (r13h[3:0]) to 1 enables the dc load discon- nect detection feature on the corresponding port. to dis- able dc load disconnect on a port, both the acd_en_ and dcd_en_ bit for that port must be set low. table 19. operating mode register table 20. port operating mode status table 21. disconnect enable register address = 12h description symbol bit no. type p4_m[1:0] 7 r/w mode[1:0] for port 4 6 r/w p3_m[1:0] 5 r/w mode[1:0] for port 3 4 r/w p2_m[1:0] 3 r/w mode[1:0] for port 2 2 r/w p1_m[1:0] 1 r/w mode[1:0] for port 1 0 r/w mode[1:0] description 00 shutdown 01 manual 10 semiautomatic 11 auto (automatic) address = 13h description symbol bit no. type acd_en4 7 r/w enable dc disconnect detection on port 4 acd_en3 6 r/w enable dc disconnect detection on port 3 acd_en2 5 r/w enable dc disconnect detection on port 2 acd_en1 4 r/w enable dc disconnect detection on port 1 dcd_en4 3 r/w enable dc disconnect detection on port 4 dcd_en3 2 r/w enable dc disconnect detection on port 3 dcd_en2 1 r/w enable dc disconnect detection on port 2 dcd_en1 0 r/w enable dc disconnect detection on port 1 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 37 detection and classification enable register (r14h) the detection and classification enable register (r14h, table 22) is used to enable detection and classification routines for the ports. on a power-up or after a reset con- dition, if auto = 1, this register is set to a default value of ffh. if auto = 0, it is set to 00h. while in auto and semiautomatic mode, setting det_e n_ (r14h[3:0]) and class_en_ (r14h[7:4]) to 1 enables load detection, and classification (upon successful detection) respectively. in manual mode, r14h works like a pushbutton register. setting a bit high launches a single detection or classification cycle, and at the con- clusion of the cycle the bit then clears. in shdn mode, programming this register has no effect. midspan enable register (r15h) the midspan enable register (r15h, table 23) is used to control cadence timing (midspan) for the ports. on a power-up or after a reset condition, this register is set to a default value of 0000?xxxx where x is the latched- in value of the midspan input. setting midspan_ (r15h[3:0]) to 1 enables cadence timing where the port backs off and waits at least 2s (min) after each failed load detection. the ieee 802.3at/af standard requires a pse that delivers power through the spare pairs (mid- span) to have cadence timing (see the midspan mode section for details). reserved register (r16h) register r16h is at this time reserved. writing to this register has no effect (the address autoincrement still updates) and any attempt to read this register returns all zeroes. table 22. detection and classification enable register table 23. midspan enable register address = 14h description symbol bit no. type class_en4 7 r/w enable classification on port 4 class_en3 6 r/w enable classification on port 3 class_en2 5 r/w enable classification on port 2 class_en1 4 r/w enable classification on port 1 det_en4 3 r/w enable detection on port 4 det_en3 2 r/w enable detection on port 3 det_en2 1 r/w enable detection on port 2 det_en1 0 r/w enable detection on port 1 address = 15h description symbol bit no. type reserved 7 ? reserved reserved 6 ? reserved reserved 5 ? reserved reserved 4 ? reserved midspan4 3 r/w enable cadence timing on port 4 midspan3 2 r/w enable cadence timing on port 3 midspan2 1 r/w enable cadence timing on port 2 midspan1 0 r/w enable cadence timing on port 1 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 38 miscellaneous configuration 1 register (r17h) the miscellaneous configuration 1 register (r17h, table 24) is used for several functions that do not cleanly fit within one of the other configuration c atego- ries. on a power-up or after a reset condition, thi s regis- ter is set to a default value of a0h. therefore, by default, int_en (r17h[7]) is set to 1 enabling int functionality. if int_en is set to 0, interrupt signals are disabl ed and int is set to a high-impedance state. if det_chg is set to 1, detect events are only be generated when the result is different from previous results (by defau lt it is set to 0). table 24. miscellaneous configuration 1 register table 25. detection/classification pushbutton register address = 17h description symbol bit no. type int_en 7 r/w a logic-high enables int functionality det_chg 6 r/w a logic-high mandates detect events are only generated when the result changes reserved 5 ? reserved reserved 4 ? reserved reserved 3 ? reserved reserved 2 ? reserved reserved 1 ? reserved reserved 0 ? reserved address = 18h description symbol bit no. type cls_pb4 7 r/w sets class_en4 in r14h to 1 cls_pb3 6 r/w sets class_en3 in r14h to 1 cls_pb2 5 r/w sets class_en2 in r14h to 1 cls_pb1 4 r/w sets class_en1 in r14h to 1 det_pb4 3 r/w sets det_en4 in r14h to 1 det_pb3 2 r/w sets det_en3 in r14h to 1 det_pb2 1 r/w sets det_en2 in r14h to 1 det_pb1 0 r/w sets det_en1 in r14h to 1 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 39 pushbutton registers (r18h?r1ah) detection/classification pushbutton register (r18h) the detection/classification pushbutton register (r18h, table 25) is used as a pushbutton to set the corre- sponding bits in the detection and classification enable register (r14h, table 22). on a power-up or after a reset condition, this register is set to a default value of 00h. power-enable pushbutton register (r19h) the power-enable pushbutton register (r19h, table 26) is used to manually power a port on or off. on a power-up or after a reset condition, this register is set to a default value of 00h. setting pwr_off_ (r19h[7:4]) to 1 turns off power to the corresponding port. pwr_off_ commands are ignored when the port is already off and during shutdown. in manual mode, setting pwr_on_ (r19h[3:0]) to 1 turns on power to the corresponding port. pwr_on_ commands are ignored in auto/semiautomatic mode, when the port is already powered, and during shutdown. after the appropriate command is executed (port power on or off), the register resets back to 00h. global pushbutton register (r1ah) the global pushbutton register (r1ah, table 27) is used to manually clear interrupts and to initiate global and port resets. on a power-up or after a reset condition, this register is set to a default value of 00h. writing a 1 to int_clr (r1ah[7]) clears all the event registers and the corresponding interrupt bits in the interrupt regis- ter (r00h, table 5). writing a 1 to pin_clr (r1ah[6]) clears the status of the int output. reset_ic (r1ah[4]) causes a global software reset, after which all registers are set back to default values (after reset condition clears). writing a 1 to reset_p_ (r1ah[3:0]) turns off power to the corresponding port and resets only the port status and event registers. if a port is powered when a reset_p_ command is initiated, the port mode is also placed into shdn, and the classification and detection enable bits are cleared. after the appropriate command is executed, the bits in the global pushbutton register all reset to 0. table 26. power-enable pushbutton register table 27. global pushbutton register address = 19h description symbol bit no. type pwr_off4 7 r/w power off port 4 pwr_off3 6 r/w power off port 3 pwr_off2 5 r/w power off port 2 pwr_off1 4 r/w power off port 1 pwr_on4 3 r/w power on port 4 pwr_on3 2 r/w power on port 3 pwr_on2 1 r/w power on port 2 pwr_on1 0 r/w power on port 1 address = 1ah description symbol bit no. type int_clr 7 r/w a logic-high clears all interrupts in event registers (r02h to r0bh) pin_clr 6 r/w a logic-high clears the int pin reserved 5 ? reserved reset_ic 4 r/w a logic-high initiates a global device reset reset_p4 3 r/w a logic-high resets port 4 reset_p3 2 r/w a logic-high resets port 3 reset_p2 1 r/w a logic-high resets port 2 reset_p1 0 r/w a logic-high resets port 1 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 40 general registers (r1bh?r1fh) id register (r1bh) the id register (r1bh, table 28) keeps track of the device id number and revision. the device?s id code is stored in id_code[4:0] (r1bh[7:3]) and is 11010. contact the factory for the value of the revision code stored in rev[2:0] (r1bh[2:0]) that corresponds to the device lot number. class 5 enable register (r1ch) the class 5 enable register (r1ch, table 29) is used to enable the classification of class 5 devices. on a power-up or after a reset condition, if en_cl5 = 0. this register is set to a default value of 00h. if en_cl5 = 1, this register is set to 0fh. class 5 classification can be enabled or disabled individually for each port in auto mode by programming the corresponding bit directly using the software. reserved register (r1dh) register r1dh is at this time reserved. writing to this register is not recommended as it is internally con- nected. if the software needs to do a large batch write command using the address autoincrement func- tion, write a code of 00h to this register to safely autoincrement past it, and then continue the write commands as normal. table 28. id register table 29. class 5 enable register address = 1bh description symbol bit no. type id_code 7 r id_code[4] 6 r id_code[3] 5 r id_code[2] 4 r id_code[1] 3 r id_code[0] rev 2 r rev[2] 1 r rev[1] 0 r rev[0] address = 1ch description symbol bit no. type reserved 7 ? reserved reserved 6 ? reserved reserved 5 ? reserved reserved 4 ? reserved cl5_en4 3 r/w set to 1 to enable class 5 classification on port 4 cl5_en3 2 r/w set to 1 to enable class 5 classification on port 3 cl5_en2 1 r/w set to 1 to enable class 5 classification on port 2 cl5_en1 0 r/w set to 1 to enable class 5 classification on port 1 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 41 tlim programming registers (r1eh and r1fh) the tlim programming registers (r1eh/r1fh, table 30) are used to adjust the t lim current-limit timeout duration. on a power-up or after a reset condition, this register is set to a default value of 00h. when tlim_[3:0] is set to 0000 the default t lim timeout is 60ms (typ). when set to any other value, the t lim timeout is set to 1.71ms times the decimal value of tlim_[3:0]. maxim reserved registers (r20h?r2fh) maxim reserved registers (r20h?r28h, r2ah?r2fh) these registers are reserved. writing to these registers is not recommended as they are internally connected. if the software needs to do a large batch write command using the address autoincrement function, write a code of 0x00h to these registers to safely autoincrement past them, and then continue the write commands as normal. miscellaneous configuration 2 register (r29h) the miscellaneous configuration 2 register (table 31) is used for several functions that do not cleanly fit within one of the other configuration categories. on a power-up or after a reset condition, this register is set to a default value of 00h. when lsc_en is set to 1, the load stabil- ity safety check is enabled and the detection phase is more immune to load variation. when vee_r_ are set to 1, v ee voltage conversion is enabled for the respective port, and the result overwrites the port voltage result in the corresponding port voltage registers. table 30. tlim programming registers table 31. miscellaneous configuration 2 register address = 1eh/1fh description symbol bit no. type tlim2/4[3:0] 7 r/w tlim timer setting for port 2/4 (1eh/1fh) 6 r/w 5 r/w 4 r/w tlim1/3[3:0] 3 r/w tlim timer setting for port 1/3 (1eh/1fh) 2 r/w 1 r/w 0 r/w address = 29h description symbol bit no. type reserved 7 ? reserved reserved 6 ? reserved reserved 5 ? reserved lsc_en 4 r/w set to 1 to enable the load stability safety check vee_r4 3 r/w enable v ee voltage readout for port 4 vee_r3 2 r/w enable v ee voltage readout for port 3 vee_r2 1 r/w enable v ee voltage readout for port 2 vee_r1 0 r/w enable v ee voltage readout for port 1 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 42 current/voltage readout registers (r30h?r3fh) port current registers (r30h, r31h, r34h, r35h, r38h, r39h, and r3ch, r3dh) the port current registers (tables 32 and 33) provi de port current readout when a port is powered on. on a power-up or after a reset condition, these regist ers are both set to a default value of 00h. the port cu rrent readout registers have 16 total bits, but the 3 hig hest bits (msbs) and the 4 lowest bits (lsbs) are hardwi red to 0. the port current readout has 9 bits of overal l actual resolution. to avoid the lsb register changing whil e reading the msb, the register contents are frozen i f addressing byte points to either of the current rea dout registers. during normal operation, the port output cur- rent can be calculated as: i out_ = n ip_ x 122.07 f a/count where n ip_ is the decimal value of the 16-bit port cur- rent readout. the adc saturates both at full scale and at zero, resulting in poor current readout accuracy near the top and bottom codes. table 32. port current register (lsb) table 33. port current register (msb) address = 30h, 34h, 38h, 3ch description symbol bit no. type ip_[7:0] 7 r ip_[7:0] (lsb). lower 8 bits of the 16-bit port current readout. ip_[3:0] are configured to be hardwired to 0. 6 r 5 r 4 r 3 r 2 r 1 r 0 r address = 31h, 35h, 39h, 3dh description symbol bit no. type ip_[15:8] 7 r ip_[15:8] (lsb). lower 8 bits of the 16-bit port current readout. ip_[15:13] are config- ured to be hardwired to 0. 6 r 5 r 4 r 3 r 2 r 1 r 0 r downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 43 port voltage registers (r32h, r33h, r36h, r37h, r3ah, r3bh, r3eh, and r3fh) the port voltage registers (tables 34 and 35) provide port voltage readout when a port is powered on. on a power-up or after a reset condition, these registers are both set to a default value of 00h. the port voltage readout registers have 16 total bits, but the 2 highest bits (msbs) and the 5 lowest bits (lsbs) are hardwired to 0. the port voltage readout has 9 bits of overall actual resolution. to avoid the lsb register changing while reading the msb, the register contents are frozen if addressing byte points to either of the voltage readout registers. during normal operation, the port output volt- age can be calculated as: v out_ = n vp_ x 5.835mv/count where n vp_ is the decimal value of the 16-bit port volt- age readout. the adc saturates both at full scale and at zero, resulting in poor voltage readout accuracy near the top and bottom codes. table 34. port voltage register (lsb) table 35. port voltage register (msb) address = 32h, 36h, 3ah, 3eh description symbol bit no. type vp_[7:0] 7 r vp_[7:0] (lsb). lower 8 bits of the 16-bit port current readout. vp_[4:0] are config- ured to be hardwired to 0. 6 r 5 r 4 r 3 r 2 r 1 r 0 r address = 33h, 37h, 3bh, 3fh description symbol bit no. type vp_[15:8] 7 r vp_[15:8] (lsb). lower 8 bits of the 16-bit port current readout. vp_[15:13] are con- figured to be hardwired to 0. 6 r 5 r 4 r 3 r 2 r 1 r 0 r downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 44 other functions registers (r00h, r01h) reserved registers (r40h, r45h, r4ah, r4fh, r54h, r59h, r5ah, r5bh, r5ch, r5dh, r5eh, r5fh) these registers are at this time reserved. writing to these registers will have no effect (the address autoincrement will still update) and any attempt to read these registers will return all zeroes. firmware register (r41h) the firmware register (r41h) is at this time set by default set to 00h. this register is provided so that it can be reprogrammed as needed by the software to indicate the version of the device firmware. watchdog register (r42h) the watchdog register (r42h, table 36) is used to monitor device status, and to enable and monitor the watchdog functionality. on a power-up or after a reset condition, this register is set to a default value of 16h. v ee_ov and v ee_uv provide supply status indepen- dent of the power status register. wd_dis[3:0] is set by default to 1011, disabling the watchdog timeout. set wd_dis[3:0] to any other value to enable the watchdog. the watchdog monitors the scl line for activity. if there are no transitions for 2.5s (typ) the wdstat bit is set to 1 and all ports are powered down (using the individual port reset protocol). wd_stat must be reset before any port can be reenabled. developer id/revision number register (r43h) the developer id/revision number register (r43h, table 37) is provided to allow developers using this device to assign the design an id and revision version number unique to their software/design. on a power-up or after a reset condition, this register is set to a default value of 00h. table 36. watchdog register table 37. developer id/revision number register address = 42h description symbol bit no. type reserved 7 r/w reserved. vee_ov 6 r/w vee_ov is set if v agnd - v ee > 62v. vee_uv 5 r/w vee_uv is set if v agnd - v ee < 40v. wd_dis[3:0] 4 r/w watchdog disable. when wd_dis[3:0] is set to 1011 (default), the watchdog is dis- abled. any other setting enables the watchdog. 3 r/w 2 r/w 1 r/w wd_stat 0 r/w wd_stat is set to 1 when the watchdog timer expires. address = 43h description symbol bit no. type dev_id[2:0] 7 r/w developer software-assigned id number 6 r/w 5 r/w reserved 4 ? reserved reserved 3 ? reserved dev_rev[2:0] 2 r/w developer software-assigned revision number 1 r/w 0 r/w downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 45 high-power enable register (r44h) the high-power enable register (r44h, table 38) is used to enable the high-power features on the ports. on power-up or after a reset condition, if auto = 1, this register is set to a default value of 0fh. if auto = 0, it is set to 00h. set hp_en_ to 1 to enable the use of the high-power features found in r46h?r58h. port gpmd register (r46h, r4bh, r50h, and r55h) the port gpmd registers (table 39) are used to enable the legacy high-capacitance pd detection and to enable 2-event classification for the corresponding port. on a power-up or after a reset condition, these registers are set to a default value of 94h. the status of the legacy input on power-up or reset is latched into the leg_en_ bit. set leg_en_ to 1 to enable, and 0 to disable, the legacy high-capacitance detection for the correspond- ing port. set pong_en_ to 1 to enable, and 0 to disable, 2-event classification. port overcurrent register (r47h, r4ch, r51h, and r56h) the port icut registers (table 40) are used to set the overcurrent sense_ voltage threshold for the corre- sponding port. on power-up or after a reset conditi on, if auto = 1, these registers are set to a default v alue of d4h. if auto = 0, it is set to 14h. to calculate th e over- current setting, take decimal value of icut[5:0] mu ltiplied times 37.5ma for cutrng = 0, and multiplied times 18.75ma for cutrng = 1 (default). multiply the resu lt by the value of the sense_ resistor (0.25 i ) to find the over- current sense_ voltage threshold. double the result ing values when calculating class 5 overcurrent thresho lds. table 38. high-power enable register table 39. port gpmd register address = 44h description symbol bit no. type reserved 7 r/w reserved reserved 6 r/w reserved reserved 5 r/w reserved reserved 4 r/w reserved hp_en4 3 r/w set to 1 to enable high-power features on port 4 hp_en3 2 r/w set to 1 to enable high-power features on port 3 hp_en2 1 r/w set to 1 to enable high-power features on port 2 hp_en1 0 r/w set to 1 to enable high-power features on port 1 address = 46h, 4bh, 50h, 55h description symbol bit no. type reserved 7 r/w reserved reserved 6 r/w reserved reserved 5 r/w reserved reserved 4 r/w reserved reserved 3 r/w reserved reserved 2 r/w reserved leg_en_ 1 r/w set to 1 to enable legacy capacitance detection on the corresponding port pong_en_ 0 r/w set to 1 to enable 2-event classification on the corresponding port downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 46 port current-limit register (r48h, r4dh, r52h, and r57h) the port current-limit registers (table 41) are use d to set the current-limit sense_ voltage threshold for the corre- sponding port. on a power-up or after a reset condi tion, these registers are set to a default value of 80h. bit 7 is hardwired to 1, while bits 5 to 0 are hardwired to 0. ilim_ (bit 6) is set to 0 for a class 0?3 pd, and to 1 fo r a class 4 or 5 pd. the state of ilim and the classification result (in the case of class 5) determine the current limi t (see the electrical characteristics table, v su_lim for details). port high-power status register (r49h, r4eh, r53h, and r58h) the port high-power status registers (table 42) are used to external fet failures and successful 2-event classification results. on a power-up or after a reset condition, these registers are set to a default value of 00h. fet_bad_ is set to 1 if the port is powered, there is no current-limit condition, and v out_ - v ee > 2v. pong_pd_ is set to 1 every time a successful 2-event classification occurs on the corresponding port. table 41. port current-limit register table 42. port high-power status register table 40. port overcurrent register address = 49h, 4eh, 53h, 58h description symbol bit no. type reserved 7 r/w reserved reserved 6 r/w reserved reserved 5 r/w reserved reserved 4 r/w reserved reserved 3 r/w reserved reserved 2 r/w reserved fet_bad_ 1 r/w set to 1 if a fet failure is detected on the corresponding port pong_pd_ 0 r/w set to 1 when a 2-event classification has occurred address = 48h, 4dh, 52h, 57h description symbol bit no. type 1 7 ? hardwired to 1 ilim_ 6 r/w current-limit setting for the corresponding port 0 5 ? hardwired to 0 0 4 ? 0 3 ? 0 2 ? 0 1 ? 0 0 ? address = 47h, 4ch, 51h, 56h description symbol bit no. type rdis_ 7 r/w sets the current-sense scale on the corresponding port; always set to 1 cut_rng_ 6 r/w icut is doubled when set to 0 icut_[5:0] 5 r/w sets the overcurrent sense_ voltage threshold (v cut ) for the corresponding port 4 r/w 3 r/w 2 r/w 1 r/w 0 r/w downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 47 ___________applications information layout procedure careful pcb layout is critical to achieve high efficiency and low emi. follow these layout guidelines for optimal performance: 1) place the high-frequency input bypass capacitor (0.1 f f ceramic capacitor from agnd to v ee ) and the output bypass capacitors (0.1 f f ceramic capacitors from agnd to out_) as close to the device as possible. 2) use large smt component pads for power dissipat- ing devices such as the max5980 and the external mosfets and sense resistors in the high-power path. 3) for the best accuracy current sensing, use kelvin- sense techniques for the sense_ and svee_ inputs in the pcb layout. the device provides individual high-side sense_ inputs for each port, and two sepa- rate shared low-side sense returns, svee1 (ports 1 and 2 low-side sense input) and svee2 (ports 3 and 4 low-side sense input). the high-side sensing should be done from the end of the high-side sense resistor pad, and the svee_ pairs should be routed from the end of the low-side sense resistor pads. to minimize the impact from additional series resistance, the two end points should be as close as possible, and sense trace length should be minimized (see figure 14 for a layout diagram, and refer to the max5980 evaluation kit for a design example). 4) use short, wide traces whenever possible for high- power paths. 5) use the max5980 evaluation kit as a design and layout reference. 6) the exposed pad (ep) must be soldered evenly to the pcb ground plane (v ee ) for proper operation and power dissipation. use multiple vias beneath the exposed pad for maximum heat dissipation. a 1.0mm to 1.2mm pitch is the recommended spacing for these vias and they should be plated (1oz copper) with a small barrel diameter (0.30mm to 0.33mm). figure 14. kelvin-sense layout diagram kelvin-sense traces to high-side/low-side sense inputs sense1 sense2 r sense1 r sense2 port current path vias to v ee port current path r sense4 r sense3 sense3 sense4 svee1 svee2 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet 48 process information process: cmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. typical operating circuit 0.25 i 1% dgnd internal pullup to v dd v ee svee1 svee2 fdmc3612 100v, 110m i sense4 gate4 out4 sense3 gate3 out3 sense2 gate2 out2 sense1 gate1 out1 0.25 i 1% 0.1f100v 0.1f100v smbj51a fdmc3612 100v, 110m i a3 a2 a1 a0 agnd -54v auto internal pullup to v dd (auto mode by default) midspan internal pullup to v dd (midspan mode by default) en_cl5 internal pulldown to dgnd (class 5 disabled by default) 0.25 i 1% fdmc3612 100v, 110m i 0.25 i 1% fdmc3612 100v, 110m i port 4 output 0.1f100v smbj51a port 3 output 0.1f100v smbj51a port 2 output 0.1f100v smbj51a port 1 output max5980 en 3k i 3k i scl 3k i int 3k i 3k i 1.8k i 50 i 33nf current sharing with other max5980 sdain sdaout v dd 200 i optional buffer external isolated serial interface hpcl063l -54v scl 200 i optional buffer hpcl063l -54v sda 200 i optional buffer hpcl063l gnd 3.3v 200 i -54v -54v package type package code outline no. land pattern no. 32 tqfn-ep t3255+4 21-0140 90-0012 downloaded from: http:///
max5980 quad, ieee 802.3at/af pse controller for power-over-ethernet revision history maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 49 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision number revision date description pages changed 0 12/10 initial release ? 1 8/11 globally changed operating temperature range to -40 c to +105 c throughout data sheet. added conditions to offset error and gain error in the electrical characteristics table . replaced tocs 1, 3, 4, 5, 8, and added toc 5b. 1?11, 13,15, 45, 46 downloaded from: http:///

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